ARM.SoC.Architecture

Arm organization and implementation summary of

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Unformatted text preview: pipelines and separate instruction and data memories (usually in the form of separate caches which are connected to a shared instruction and data main memory system). This chapter includes descriptions of the internal structures of these two basic styles of processor core and covers the general principles of operation of the 3-stage and 5-stage pipelines and a number of implementation details. Details on particular cores are presented in Chapter 9. 74 3-stage pipeline ARM organization 75 4.1 3-stage pipeline ARM organization The organization of an ARM with a 3-stage pipeline is illustrated in Figure 4.1 on page 76. The principal components are: The register bank, which stores the processor state. It has two read ports and one write port which can each be used to access any register, plus an additional read port and an additional write port that give special access to r15, the program counter. (The additional write port on r15 allows it to be updated as the instruc tion fetch address is incremented and the read port allows instruction fetch to resume after a data address has been issued.) The barrel shifter, which can shift or rotate one operand by any number of bits. The ALU, which performs the arithmetic and logic functions required by the instruction set. The address register and incrementer, which select and hold all memory addresses and generate sequential addresses when required. The data registers, which hold data passing to and from memory. The instruction decoder and associated control logic. In a single-cycle data processing instruction, two register operands are accessed, the value on the B bus is shifted and combined with the value on the A bus in the ALU, then the result is written back into the register bank. The program counter value is in the address register, from where it is fed into the incrementer, then the incremented value is copied back into rl5 in the register bank and also into the address register to be used as the address for the next instruction fetch. The 3-stage pipeline ARM processors up to the ARM? employ a simple 3-stage pipeline with the following pipeline st...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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