ARM.SoC.Architecture

Arm cores are very small typically occupying just a

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Unformatted text preview: ved from the first ARM core to implement the 32-bit address space programming model, the ARM6, which it now supersedes. The ARM6 used circuit techniques that prevented it from operating reliably with a power supply of less than 5 volts. The ARM? corrected this deficiency, and then 64-bit multiply instructions, on-chip debug support, the Thumb instruction set and the EmbeddedlCE watchpoint hardware were all added over a fairly short period of time to give the ARM7TDMI. The origins of the name are as follows: The ARM7, a 3 volt compatible rework of the ARM6 32-bit integer core, with: the Thumb 16-bit compressed instruction set; on-chip Debug support, enabling the processor to halt in response to a debug request; an enhanced Multiplier, with higher performance than its predecessors and yield ing a full 64-bit result; and EmbeddedlCE hardware to give on-chip breakpoint and watchpoint support. The ARM7TDMI has been fabricated on a large number of different CMOS process technologies, some supporting clock rates over 100 MHz and others enabling operation at 0.9 V (thereby allowing a single-cell battery to be used as the source of power). Typical applications in production at the time of writing use a 3.3 V supply on a 0.35 um process yielding a clock rate of up to 66 MHz, but the trend is, of course, towards smaller transistors, lower supply voltages and higher clock frequencies. ARM7TDMI organization The organization of the ARM7TDMI is illustrated in Figure 9.1 on page 249. The ARM7TDMI core is a basic ARM integer core using a 3-stage pipeline (see Section 4.1 on page 75) with a number of important features and extensions: It implements ARM architecture version 4T, with support for 64-bit result multi plies, half-word and signed byte loads and stores and the Thumb instruction set. It includes the EmbeddedlCE module to support embedded system debugging. (This was described in Section 8.7 on page 232.) As the debug hardware is accessed via the JTAG test access port, the JTAG control logic (described in Section 8.6 on p...
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