ARM.SoC.Architecture

Arm10tdmi 263 5 arm7tdmi 249 arms 256 clock skew 375

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Unformatted text preview: TAG instruction) 229,231 fan-in (of logic gates) 399 Fast Interrupt Request (FIQ) 313 finite state machine (FSM) 9 FIQ (Fast Interrupt Request) 313 floating-point ARM architecture 163-8 datatypes 158-63,342-3 registers 165-6,311 units 360-1 FPA 10 coprocessor 163-8,360-1 VFP10 coprocessor 168, 342-3 for loops 173 forwarding paths 331 FPA 10 data types 163-8,360-1 fully associative cache 277-8 functions 157, 175-80 gate abstraction 5-6 gate-level design 6-7 gated clocks 30 416 Index half-word data transfer instructions 127-9 hardware prototyping 223-4 heap 180 Hello World program 69-71 hexadecimal notation 154 high-level languages 151-85 Harvard cache 272 hazard, read-after-write 22 hard macrocells 100-1 'Halt'instruction 383-4 hierarchy of components 175 swap memory and register instructions (SWP) 132-3 types of 16 unused instruction space 142-3 usage measurements 21 see also branch instructions; Thumb instruction set integer unit organization 258, 259 integers 155 interrupt controller 222 interrupt latency 313 INTEST (JTAG instruction) 229 IRQ 107-10 ISDN Subscriber Processor 349-52 JTAG boundary scan test architecture 226-32,254 jump tables 67-8 jump trace buffer 382-3 JumpStart tools 47 keyboard interfaces 351 latches 402-3 late aborts 161 latency 313,314 LDM data abort 145 leaf routines 175--6 level signalling 377 libraries 185 line length 345 link register 66 linker 45 little-endian 41, 106-7, 157 load instructions 57-8 load-store architecture 41, 165 logic combinatorial 402 computer logic 399 control logic 10-11,209-11 design 8-9 PLA (programmable logic array) 99 symbols 5 logic gates 4-5, 399-400 logical operations 51 loops 173^t low power see power management macrocells 100-1 testing 230-2 MARBLE on-chip bus 392 memory 180-4 address space model 180-1 bandwidth 344 double-bandwidth 257 bottlenecks 79 content addressed memory (CAM) 277, 281-2 controllers 340,361,369 cost 270 Direct Memory Access (DMA) 312-13 DRAM (dynamic random access memory) 213-14, 215, 272 efficiency 183-4 external memory interface 392-3 faults 143-7 hit-under-miss support 341 I/O (input/output) 42-3,312-15,361 IDCODE (JTAG instruction) 229 idempotency 103,312 IEEE 754 Standard 159 if...else 170-1 immediate addressing 17 im...
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