ARM.SoC.Architecture

Arm810 silicon a photograph of an arm810 die is shown

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Unformatted text preview: scan test circuitry for testing printed circuit board connectivity (the JTAG 'in-test', for in-circuit testing of the device itself, is not supported). The first StrongARM chips are implemented on Digital's 0.35 um CMOS process, using three layers of metal. They use around 2.5 million transistors on a 50 mm2 die (which is very small for a processor of this performance) and deliver 200 to 250 Dhrystone MIPS with a 160 to 200 MHz clock, dissipating half to just under one watt using a 1.65 V to 2 V supply. 328 ARM CPU Cores Figure 12.7 StrongARM organization. The StrongARM processor core The processor core employs a 'classic' 5-stage pipeline with full bypassing (register forwarding) and hardware interlocks. The ARM instruction set requires some instruction decoding to take place before the register bank read accesses can begin, and it also requires a shift operation in series with the ALU, but both of these addi- The Strong ARM SA-110 329 tional logic functions are fitted within their respective pipeline stages and do not add to the pipeline depth. The pipeline stages are: 1. Instruction fetch (from the instruction cache). 2. Instruction decode and register read; branch target calculation and execution. 3. Shift and ALU operation, including data transfer memory address calculation. 4. Data cache access. 5. Result write-back to register file. The organization of the major pipeline components is illustrated in Figure 12.8 on page 330. The shaded bars delimit the pipeline stages and data which passes across these bars will be latched at the crossing point. Data which feeds around the end of a bar is being passed back or forward across pipeline stages, for example: The register forwarding paths which pass intermediate results on to following instructions to avoid a register interlock stall caused by a read-after-write hazard. The PC path which forwards pc + 4 from the fetch stage of the next instruction, giving pc + 8 for the current instruction, to be used as r15 and in the branch target ca...
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