ARM.SoC.Architecture

All the data processing instructions that operate

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: er transfer instructions, and have exactly the same semantics as the ARM equivalent. In all cases the offset is scaled to the size of the data type, so, for instance, the range of the 5-bit offset is 32 bytes in a load or store byte instruction, 64 bytes in a load or store half-word instruction and 128 bytes in a load or store word instruction. The various assembler formats are: 1: 2: 3: A: 5: Assembler format <op> Rd, [Rn, #<#off5>] ; <Op> = LDRILDRB|STRISTRB <op> Rd, [Rn, #<#off5>] ; <op> = LDRHISTRH <op> Rd, [Rn, Rm] ; <op> = .. LDR Rd, [PC, #<#off8>] <op> Rd, [SP, #<#off8>] ; <op> = LDRISTR ; .. LDRILDRHILDRSHILDRBILDRSBISTRISTRHISTRB Thumb multiple register data transfer instructions 199 Equivalent ARM instruction Notes The ARM equivalents to these Thumb instructions have identical assembler formats. 1. #of f 5 and toff 8 denote 5- and 8-bit immediate offsets respectively. The assem bler format specifies the offset in bytes in all cases. The 5- or 8-bit offset in the instruction binary is scaled by the size of the data type. 2. As with the ARM instructions, the signed variants are only supported by the load instructions since store signed and store unsigned have exactly the same effect. 7.7 Thumb multiple register data transfer instructions As in the ARM instruction set, the Thumb multiple register transfer instructions are useful both for procedure entry and return and for memory block copy. Here, however, the tighter encoding means that the two uses must be separated and the number of addressing modes restricted. Otherwise these instructions very much follow the spirit of their ARM equivalents. Binary encodings Figure 7.6 Thumb multiple register data transfer binary encodings. Description The block copy forms of the instruction use the LDMIA and STMIA addressing modes (see Figure 3.2 on page 62). The base register may be any of the 'Lo' registers (r0 to r7), and the register list may include any subset of these registers but should not include the base register itself since write-back is always selected (and the...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online