Allowing the pc to be saved in order to support a

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: from if the objective is to design a high-performance processor which is a good compiler target. Figure 1.7 MU0 ALU logic for one bit. 14 An Introduction to Processor Design 1.4 Instruction set design If the MU0 instruction set is not a good choice for a high-performance processor, what other choices are there? Starting from first principles, let us look at a basic machine operation such as an instruction to add two numbers to produce a result. 4-addreSS instructions In its most general form, this instruction requires some bits to differentiate it from other instructions, some bits to specify the operand addresses, some bits to specify where the result should be placed (the destination), and some bits to specify the address of the next instruction to be executed. An assembly language format for such an instruction might be: ADD s2 d, s1, s2, next_i ; d := s1 + Such an instruction might be represented in memory by a binary format such as that shown in Figure 1.8. This format requires 4n +f bits per instruction where each operand requires n bits and the opcode that specifies 'ADD' requires/bits. Figure 1.8 A 4-address instruction format. 3-addresS instructions The first way to reduce the number of bits required for each instruction is to make the address of the next instruction implicit (except for branch instructions, whose role is to modify the instruction sequence explicitly). If we assume that the default next instruction can be found by adding the size of the instruction to the PC, we get a 3-address instruction with an assembly language format like this: ADD d, s1, s2 ; d := s1 + s2 A binary representation of such an instruction is shown in Figure 1.9. Figure 1.9 A 3-address instruction format. 2-addreSS instructions A further saving in the number of bits required to store an instruction can be achieved by making the destination register the same as one of the source registers. The assembly language format could be: Instruction set design 15 ADD d, s1 ; d := d + s1 The binary representation now reduces to that shown in Figure 1.10. Figure 1.10 A 2-address instruction format. 1...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online