ARM.SoC.Architecture

Although this interfacing is not particularly

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: der form of system bus, with AHB being introduced later to improve support for higher performance, synthesis and timing verification. The APB is generally used as a local secondary bus which appears as a single slave module on the AHB or ASB. In the following sections we assume the system bus is an ASB. More details on the AHB are provided at the end of the section. Arbitration A bus transaction is initiated by a bus master which requests access from a central arbiter. The arbiter decides priorities when there are conflicting requests, and its design is a system specific issue. The ASB only specifies the protocol which must be followed: Figure 8.11 A typical AMBA-based system. 218 Architectural Support for System Development i The master, x, issues a request (AREQx) to the central arbiter. When the bus is available, the arbiter issues a grant (AGNTx) to the master. (The arbitration must take account of the bus lock signal (BLOK) when deciding which grant to issue to ensure that atomic bus transactions are not violated.) Bus transfers When a master has been granted access to the bus, it issues address and control information to indicate the type of the transfer and the slave device which should respond. The following signal is used to define the transaction timing: The bus clock, BCLK. This will usually be the same as mclk, the ARM processor clock. The bus master which holds the grant then proceeds with the bus transaction using the following signals: Bus transaction, BTRAN[1:0], indicates whether the next bus cycle will be address-only, sequential or non-sequential. It is enabled by the grant signal and is ahead of the bus cycle to which it refers. The address bus, BA[31:OJ. (Not all address lines need be implemented in sys tems with modest address-space requirements, and in a multiplexed implementa tion the address is sent down the data bus.) Bus transfer direction, BWRITE. Bus protection signals, BPROT[1:0], which indicate instruction or data fetches and superviso...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online