ARM.SoC.Architecture

An interrupt from the serial line hardware device

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Unformatted text preview: ched in, running up a large bill on a system with accounting. Exercise 11.1.1 What minimum level of protection must be applied to the bottom of memory (where the exceptions vectors are located) in a secure operating system? If the ARM had no SWAP instruction, devise a hardware peripheral that could be used to support synchronization. (Hint: standard memory will not work; the location must be read-sensitive.) Exercise 11.1.2 ARM CPU Cores Summary of chapter contents Although some ARM applications use a simple integer processor core as the basic processing component, others require tightly coupled functions such as cache memory and memory management hardware. ARM Limited offers a range of such 'CPU' configurations based around its integer cores. The ARM CPU cores described here include the ARM710T, 720T and 740T, the ARM810 (now superseded by the ARM9 series), the StrongARM, the ARM920T and 940T, and the ARM1020E. These CPUs encompass a range of pipeline and cache organizations and form a useful illustration of the issues which arise when designing high-performance processors for low-power applications. The primary role of a cache memory is to satisfy the processor core's instruction and data bandwidth requirements, so the cache organization is tightly coupled to the particular processor core that it is to serve. In the context of system-on-chip designs the goal is for the cache to reduce the external memory bandwidth requirements of the CPU core to a level that can be handled by an on-chip bus. The higher-performance ARM processor cores would run little faster than the ARM7TDMI if they were connected directly to an AMBA bus, so they will always be used with fast local memory or cache. Memory management is another complex system function that must be tightly coupled to the processor core, whether it is a full translation-based system or a simpler protection unit. The ARM CPU cores integrate the processor core, cache(s), MMU(s) and (usually) an AMBA interface in a single macrocell. 317 318 ARM CPU Cores 12.1 The ARM710T, ARM720T and ARM740T The ARM710T, ARM720T and ARM740T are based upon the ARM7TDMI processor core (see Section 9.1 on page 248), to which an 8 Kbyte mixed instruction...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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