ARM.SoC.Architecture

Arithmetic operations are down at 15 as are

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Unformatted text preview: covered in Section 10.3 on page 272. A third technique, super-scalar instruction execution, is very complex, has not been used on ARM processors and is not covered in this book. 22 An Introduction to Processor Design Pipelines A processor executes an individual instruction in a sequence of steps. A typical sequence might be: 1. Fetch the instruction from memory (fetch). 2. Decode it to see what sort of instruction it is (dec). 3. Access any operands that may be required from the register bank (reg). 4. Combine the operands to form the result or a memory address (ALU). 5. Access memory for a data operand, if necessary (mem). 6. Write the result back to the register bank (res). Not all instructions will require every step, but most instructions will require most of them. These steps tend to use different hardware functions, for instance the ALU is probably only used in step 4. Therefore, if an instruction does not start before its predecessor has finished, only a small proportion of the processor hardware will be in use in any step. An obvious way to improve the utilization of the hardware resources, and also the processor throughput, would be to start the next instruction before the current one has finished. This technique is called pipelining, and is a very effective way of exploiting concurrency in a general-purpose processor. Taking the above sequence of operations, the processor is organized so that as soon as one instruction has completed step 1 and moved on to step 2, the next instruction begins step 1. This is illustrated in Figure 1.13. In principle such a pipeline should deliver a six times speed-up compared with non-overlapped instruction execution; in practice things do not work out quite so well for reasons we will see below. Pipeline hazards It is relatively frequent in typical computer programs that the result from one instruction is used as an operand by the next instruction. When this occurs the pipeline operation shown in Figure 1.13 breaks down, since the result of instruction 1 is not available at the...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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