ARM.SoC.Architecture

As with instruction and data caches described in

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Unformatted text preview: s the fact that a paging MMU only affects the high-order address bits, while the cache is accessed by the low-order address bits. Provided these sets do not overlap, the cache and MMU accesses can proceed in parallel. The physical address from the MMU arrives at the right time to be compared with the physical address tags from the cache, hiding the address translation time behind the cache tag access. This optimization is not applicable to fully associative caches, and only works if the page size used by the MMU is larger than each directly addressed portion of the cache. A 4 Kbyte page, for example, limits a direct-mapped cache to a maximum size of 4 Kbytes, a 2-way set-associative cache to a maximum size of 8 Kbytes, and so on. In practice both virtual and physical caches are in commercial use, the former relying on software conventions to contain the synonym problem and the latter either exploiting the above optimization or accepting the performance cost. Examples and exercises 289 10.6 Examples and exercises How big can a 4-way physical cache be in a system with 1 Kbyte pages? Assume we want to perform the TLB and cache accesses in parallel as described in 'Virtual and physical caches' on page 287. Each section of the cache can be at most 1 Kbyte, so the maximum total cache size is 4 Kbytes. How much memory does the tag store require in this cache if the line size is 16 bytes? Estimate the proportions of the areas of the TLB and the data cache tag and data memories in the above example. How big would a TLB have to be to contain the translations for all of the physical pages? With 4 Kbyte pages, a 1 Mbyte memory contains 256 pages so the TLB needs 256 entries. The TLB need no longer be an automatic cache. Since a TLB miss means that the page is absent from physical memory a disk transfer is required, and the overhead of maintaining the TLB by software is negligible compared with the cost of the disk transfer. A TLB which covers all physical memory is a form of inverted page table, and just such a transl...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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