ARM.SoC.Architecture

Asynchronous circuits emit less electromagnetic

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Unformatted text preview: power-efficient. However, the CMOS circuits used to implement transition control are relatively slow and inefficient, so AMULET2 and AMULETS use level signalling which employs circuits which are faster and more power-efficient despite using twice the number of transitions, but leave somewhat arbitrary decisions to be taken about the timing of the recovery (return-to-zero) phases in the protocol. Self-timed pipelines An asynchronous pipelined processing unit can be constructed using self-timing techniques to allow for the processing delay in each stage and one of the above protocols to send the result to the next stage. When the circuit is correctly designed variable processing and external delays can be accommodated; all that matters is the local sequencing of events (though long delays will, of course, lead to low performance). Unlike a clocked pipeline, where the whole pipeline must always be clocked at a rate determined by the slowest stage under worst-case environmental (voltage and temperature) conditions and assuming worst-case data, an asynchronous pipeline will operate at a variable rate determined by current conditions. It is possible to allow rare worst-case conditions to cause a processing unit to take a little longer. There will be some performance loss when these conditions do arise, but so long as they are rare enough the impact on overall performance will be small. 14.2 AMULET1 The AMULET 1 processor core has the high-level organization illustrated in Figure 14.3 on page 378. The design is based upon a set of interacting asynchronous 378 The AMULET Asynchronous ARM Processors Figure 14.3 AMULET1 internal organization. pipelines, all operating in their own time at their own speed. These pipelines might appear to introduce unacceptably long latencies into the processor but, unlike a synchronous pipeline, an asynchronous pipeline can have a very low latency. The operation of the processor begins with the address interface issuing instruction fetch requests to the memory. The address interface has an autonomous address incre-menter which enables it to pre...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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