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Unformatted text preview: > Rn, Rm Rm Rn Rm, #<#sh> Thumb data processing instructions 197 ; ARM instruction MOVS MOVS MOVS MOVS MOVS MOVS ANDS EORS ORRS BICS MULS Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rm, Rd, Rm, Rd, Rd, Rd, Rd, Rd, Rd, Rm, LSL LSR LSR ASR ASR ROR Rm Rm Rm Rm Rd Rs #<#sh> Rs #<#sh> Rs Rs Thumb instruction ; LSL ; LSR ; LSR ; ASR ; ASR ; ROR ; AND ; EOR ; ORR ; BIG ; MUL Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rd, Rs Rm, #<#sh> Rs Rm, #<#sh> Rs Rs Rm Rm Rm Rm Rm Instructions that operate with or on the 'Hi' registers (r8 to r15), in some cases in combination with a 'Lo' register:
; ARM instruction ADD CMP MOV ADD ADD ADD SUB Rd, Rd, Rm Rn, Rm Rd, Rm Rd, PC, #<#imm8> Rd, SP, #<#imm8> SP, SP, #<#imm7> SP, SP, #<#imm7> Thumb instruction ; ADD Rd, Rm ; CMP Rn, Rm ; MOV Rd, Rm ; ADD Rd, PC, ; ADD Rd, SP, ; ADD SP, SP, ; SUB SP, SP, (1/2 Hi regs) (1/2 Hi regs) (1/2 Hi regs) #<#imm8> #<#imm8> #<#imm7> #<#imm7> Notes 1. All the data processing instructions that operate with and on the 'Lo' registers update the condition code bits (the S bit is set in the equivalent ARM instruc tion). 2. The instructions that operate with and on the 'Hi' registers do not change the condition code bits, with the exception of CMP which only changes the condi tion codes. 3. The instructions that are indicated above as requiring '1 or 2 Hi regs' must have one or both register operands specified in the 'Hi' register area. 4. #imm3, #imm7 and #imm8 denote 3-, 7- and 8-bit immediate fields respectively. #sh denotes a 5-bit shift amount field. 198 The Thumb Instruction Set 7.6 Thumb single register data transfer instructions
Again the choice of ARM instructions which are represented in the Thumb instruction set appears complex, but is based on the sort of things that compilers like to do frequently. Note the larger offsets for accesses to the literal pool (PC-relative) and to the stack (SP-relative), and the restricted support given to signed operands (base plus register addressing only) compared with unsigned operands (base plus offset or register). Binary encodings Figure 7.5 Thumb single register data transfer binary encodings. Description These instructions are a carefully derived subset of the ARM single regist...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09