But we appear to have lost the base register a long

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Unformatted text preview: ata aborts was added fairly late in the development of the first ARM processor chip. Up to that point, the various load and store multiple addressing modes had been implemented starting from the base address and incrementing up or decrementing down memory according to the mode. The chip was therefore designed with an address incrementer/decrementer unit. When it became clear that support for virtual memory was needed it was rapidly seen that the decrementing mode made abort recovery much harder, since the PC could be overwritten before the abort was signalled. Therefore the implementation was changed always to increment the address. The memory addresses used were the same, and the mapping of register to memory was unchanged (see Figure 3.2 on page 62); just the order of the transfer was changed to lowest address first, PC last. This change was implemented too late to affect the layout of the address generating logic, so the first ARM silicon has an address incrementer/decrementer hard-wired always to increment. Needless to say, this redundancy was not carried forward to subsequent implementations. The earlier a processor gets an indication of a fault from the memory system, the better placed it is to preserve state. The earlier a processor requires the fault signal, the harder the memory system is to design. There is therefore a tension between the architectural simplicity of the processor's fault handling and the engineering efficiency of the memory system. This tension doesn't affect just the memory management unit. Where the processor has a cache memory, the cache design can also be affected by the abort timing. Early ARM processors required the abort signal by the end of phase 1 of the clock cycle (see Figure 4.8 on page 86), before half-way through the memory access. A fully associative cache with a CAM-RAM (CAM is Content Addressable Memory) organization can be designed to generate its hit/miss signal from the CAM access only, in time either to confirm a satisfactory access or to halt the processor in phase 1. Onc...
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