ARM.SoC.Architecture

D is set on a data breakpoint register 6 which is

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Unformatted text preview: lso to have separate instruction and data TLBs. Memory granularity The memory mapping is performed at several different granularities by the same basic mechanism. The units that can be used are: Sections. These are 1 Mbyte blocks of memory. Large pages. These are 64 Kbyte blocks of memory, and within a large page access control is applied to individual 16 Kbyte subpages. Small pages. These are 4 Kbyte blocks of memory, and within a small page access control is applied to individual 1 Kbyte subpages. Tiny pages. Some of the latest CPUs also support 1 Kbyte 'tiny' pages. The normal granularity is the 4 Kbyte small page. Large pages and sections exist to allow the mapping of large data areas with a single TLB entry. Forcing a large data area to be mapped in small pages can, under certain circumstances, cause the TLB to perform inefficiently. Domains Domains are an unusual feature of the ARM MMU architecture. A domain is a group of sections and/or pages which have particular access permissions. This allows a number of different processes to run with the same translation tables while retaining some protection from each other. It gives a much more lightweight process switch mechanism than is possible if each process must have its own translation tables. ARM MMU architecture 303 The access control is based on two sorts of programs: Clients are users of domains and must observe the access permissions of the individual sections and pages that make up the domain. Managers are the controllers of the domain and can bypass the access permissions of individual sections or pages. Table 11.4 Value Status No access Client Reserved Manager Description Any access will generate a domain fault Page and section permission bits are checked Do not use Page and section permission bits are not checked Domain access control bits. 00 01 10 11 At any one time a program may be a client of some domains, a manager of some other domains and have no access at all to the remaining domains. This is controlled by CP15 register 3 which contains two bits for each of the 16 domains...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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