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Unformatted text preview: agation. Arithmetic operations (addition, subtraction and comparisons) involve longer logic paths as the carry can propagate across the word width. Adder design Since the 32bit addition time has a significant effect on the datapath cycle time, and hence the maximum clock rate and the processor's performance, it has been the focus of considerable attention during the development of successive versions of the ARM processor. 88 ARM Organization and Implementation Figure 4.10 The original ARM1 ripplecarry adder circuit. The first ARM processor prototype used a simple ripplecarry adder as shown in Figure 4.10. Using a CMOS ANDORINVERT gate for the carry logic and alternating AND/OR logic so that even bits use the circuit shown and odd bits use the dual circuit with inverted inputs and outputs and AND and OR gates swapped around, the worstcase carry path is 32 gates long. In order to allow a higher clock rate, ARM2 used a 4bit carry lookahead scheme to reduce the worstcase carry path length. The circuit is shown in Figure 4.11 on page 89. The logic produces carry generate (G) and propagate (P) signals which control the 4bit carryout. The carry propagate path length is reduced to eight gate delays, again using merged ANDORINVERT gates and alternating AND/OR logic.
ALU functions The ALU does not only add its two inputs. It must perform the full set of data operations defined by the instruction set, including address computations for memory transfers, branch calculations, bitwise logical functions, and so on. The full ARM2 ALU logic is illustrated in Figure 4.12 on page 89. The set of functions generated by this ALU and the associated values of the ALU function selects are listed in Table 4.1 on page 90. A further improvement in the worstcase add time was introduced on the ARM6 by using a carryselect adder. This form of adder computes the sums of various fields of the word for a carryin of both zero and one, and then the final result is selected by using the correct carryin value to control a multiplexer. The overall scheme is illustrated in Figure 4.13 on page 90. The...
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 Spring '09
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