ARM.SoC.Architecture

External hardware is informed of when the core is in

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Unformatted text preview: to the JTAG system, along with the boundary scan extension signals detailed below. tapsm[3:0] indicates the state the TAP controller is in; ir[3:0] gives the contents of the TAP instruction register; screg[3:0] is the address of the scan register currently selected by the TAP controller; tckl and tck2 form a non-overlapping pair of clocks to control extension scan chains, and tdoen indicates when serial data is being driven out on tdo. The ARM7TDMI cell contains a full JTAG TAP controller to support the Embed-dedlCE functionality, and this TAP controller is capable of supporting any other on-chip scan facilities that are accessed through the JTAG port. The drivebs, ecapclkbs, icapclkbs, highz, pclkbs, rstclkbs, sdinbs, sdoutbs, shclkbs and shclk2bs interface signals are therefore made available to allow arbitrary additional scan paths to be added to the system. The reader should refer to the relevant ARM7TDMI datasheet for details of the individual functions of these signals. A plot of the ARM7TDMI processor core is shown in Figure 9.4 on page 255. The characteristics of the 0.35 um core when executing 32-bit ARM code are summarized in Table 9.2. On a suitable process technology exceedingly high power-efficiencies have been obtained with ARM7TDMI cores. One example used a 0.25 um process technology with a 0.9 V power supply to deliver 12,000 MIPS/W. Power JTAG interface TAP information Boundary scan extension ARM7TDMI core ARM7TDMI 255 1 j oc < Figure 9.4 Table 9.2 Process Metal layers The ARM7TDMI processor core. ARM7TDMI characteristics. 74,209 MIPS 2.1 mm2 Power 0-66 MHz MIPSAV 0.35 urn Transistors 3 Core area 60 87 mW Vdd 3.3V Clock 690 ARM7TDMI for synthesis The standard ARM7TDMI processor core is a 'hard' macrocell, which is to say that it is delivered as a piece of physical layout, customized to the appropriate process technology. The ARM7TDMI-S is a synthesizable version of the ARM7TDMI, delivered as a high-level language module which can be synthesized using any suitable cell library in the target technology. It is therefo...
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