ARM.SoC.Architecture

External logic can then look at the previous address

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Unformatted text preview: so early. Typical timing is illustrated in Figure 8.10. (wait is inactive during this sequence.) 216 Architectural Support for System Development Figure 8.10 DRAM timing after an internal cycle. Peripheral access Most systems incorporate peripheral devices in addition to the memory components described so far. These often have slow access speeds, but can be interfaced using techniques similar to those described above for ROM access. 8.2 The Advanced Microcontroller Bus Architecture (AMBA) ARM processor cores have bus interfaces that are optimized for high-speed cache interfacing. Where a core is used, with or without a cache, as a component on a complex system chip, some interfacing is required to allow the ARM to communicate with other on-chip macrocells. Although this interfacing is not particularly difficult to design, there are many potential solutions. Making an ad hoc choice in every case consumes design resource and inhibits the reuse of peripheral macrocells. To avoid this waste, ARM Limited specified the Advanced Microcontroller Bus Architecture, AMBA, to standardize the on-chip connection of different macrocells. Macrocells designed to this bus interface can be viewed as a kit of parts for future system chips, and ultimately designing a complex system on a chip based on a new combination of existing macrocells could become a straightforward task. AMBA buses Three buses are denned within the AMBA specification: The Advanced High-performance Bus (AHB) is used to connect high-performance system modules. It supports burst mode data transfers and split transactions, and all timing is reference to a single clock edge. The Advanced Microcontroller Bus Architecture (AMBA) 217 The Advanced System Bus (ASB) is used to connect high-performance system modules. It supports burst mode data transfers. The Advanced Peripheral Bus (APB) offers a simpler interface for low-performance peripherals. A typical AMBA-based microcontroller will incorporate either an AHB or an ASB together with an APB as illustrated in Figure 8.11. The ASB is the ol...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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