ARM.SoC.Architecture

For example add x r1 r3 r2 r1 lsl 3 r3 r2 8 note

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Unformatted text preview: The available shift operations are: LSL: logical shift left by 0 to 31 places; fill the vacated bits at the least significant end of the word with zeros. LSR: logical shift right by 0 to 32 places; fill the vacated bits at the most signifi cant end of the word with zeros. ASL: arithmetic shift left; this is a synonym for LSL. ASR: arithmetic shift right by 0 to 32 places; fill the vacated bits at the most sig nificant end of the word with zeros if the source operand was positive, or with ones if the source operand was negative. ROR: rotate right by 0 to 32 places; the bits which fall off the least significant end of the word are used, in order, to fill the vacated bits at the most significant end of the word. RRX: rotate right extended by 1 place; the vacated bit (bit 31) is filled with the old value of the C flag and the operand is shifted one place to the right. With appropriate use of the condition codes (see below) a 33-bit rotate of the operand and the C flag is performed. These shift operations are illustrated in Figure 3.1 on page 54. It is also possible to use a register value to specify the number of bits the second operand should be shifted by: ADD x 2r2 r5, r5, r3, LSL r2 ; r5 := r5 + r3 This is a 4-address instruction. Only the bottom eight bits of r2 are significant, but since shifts by more than 32 bits are not very useful this limitation is not important for most purposes. Setting the condition codes Any data processing instruction can set the condition codes (N, Z, C and V) if the programmer wishes it to. The comparison operations only set the condition codes, so there is no option with them, but for all other data processing instructions a 54 ARM Assembly Language Programming Figure 3.1 ARM shift operations specific request must be made. At the assembly language level this request is indicated by adding an 's' to the opcode, standing for 'Set condition codes'. As an example, the following code performs a 64-bit addition of two numbers held in r0-r1 and r2-r3, using the C condition code flag to store the intermediate carry: Since the s opcode ext...
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