Here it is very important to ensure that only one

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Unformatted text preview: r register transfer cycles. Wait states If we try to speed up the clock in this system it will stop working when the slowest path fails. This will normally be the ROM access. We can get a lot more performance from the system if the clock is tuned to the RAM access time and wait states are introduced to allow the ROM more access time. Usually the ROM will be allowed a fixed number of clock cycles per access, the exact number being determined by the clock rate and the ROM data sheet. We will assume an access time of four clock cycles. The memory control logic must now incorporate a simple finite state machine to control the ROM access. A suitable state transition diagram is shown in Figure 8.3. Figure 8.3 ROM wait control state transition diagram. 212 Architectural Support for System Development The three ROM states are used to stretch the ROM access time to four cycles by asserting the ARM's wait input. A design problem here is that since the addresses have been retimed to become valid early in the current cycle and wait must be asserted before mclk rises, wait cannot be generated as a simple state machine output since there is no clock edge that can be used to generate it. Another problem is to generate a stretched ROMoe signal that is glitch-free. A possible circuit is shown in Figure 8.4. The state machine is a synchronous counter which uses the two edge-triggered flip-flops. Only the state ROM3 is of significance, since it de-activates wait which is otherwise active whenever a ROM access is detected. The two level-sensitive latches are used to generate a clean, stretched ROMoe using wait as the starting point. A timing diagram for this circuit is shown in Figure 8.5 on page 213, which should clarify the operation of the logic. Sequential accesses If the system is to operate even faster it may not be possible to decode a new address and perform a RAM access in a single clock cycle. Here an extra cycle can be inserted whenever an unknown address is issued to allow time for address de...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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