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Unformatted text preview: ADD or SUB instruction.) As an example, consider a program which must copy data from TABLE 1 to TABLE2, both of which are near to the code: Here we have introduced labels (COPY, TABLE1 and TABLE2) which are simply names given to particular points in the assembly code. The first ADR pseudo instruction causes r1 to contain the address of the data that follows TABLE1; the second ADR likewise causes r2 to hold the address of the memory starting at TABLE2. Of course any ARM instruction can be used to compute the address of a data item in memory, but for the purposes of small programs the ADR pseudo instruction will do what we require. Single register load and store instructions These instructions compute an address for the transfer using a base register, which should contain an address near to the target address, and an offset which may be another register or an immediate value. We have just seen the simplest form of these instructions, which does not use an offset:
LDR [r1] STR [r1] r0, r0, ; r0 := mem32 [r1] ; mem32[r1] := r0 The notation used here indicates that the data quantity is the 32-bit memory word addressed by r1. The word address in r1 should be aligned on a 4-byte boundary, so the two least significant bits of r1 should be zero. We can now copy the first word from one table to the other: 58 ARM Assembly Language Programming We could now use data processing instructions to modify both base registers ready for the next transfer: Note that the base registers are incremented by 4 (bytes), since this is the size of a word. If the base register was word-aligned before the increment, it will be word-aligned afterwards too. All load and store instructions could use just this simple form of register-indirect addressing. However, the ARM instruction set includes more addressing modes that can make the code more efficient. Base plus offset addressing If the base register does not contain exactly the right address, an offset of up to 4 Kbytes may be added (or subtracted) to the base to compute the transfer address:
LDR r0, [r1,#4] ; + r0 4] := men32[r1 This is a pre-indexed addressing mode. It allows one base r...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09