If context switches may take place in response to

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Unformatted text preview: instruction or write-through data cache can be flushed simply by marking all entries as invalid, which on an ARM processor chip requires a single CP15 instruction for each TLB or cache, but a copy-back cache must be purged of all dirty lines which may take many instructions. (Note that a physically addressed cache avoids this problem, but to date all ARM CPUs have used virtually addressed caches.) Where the old and new processes share the same translation tables a light-weight process switch is required. The 'domain' mechanism in the ARM MMU architecture allows the protection state of 16 different subsets of the virtual address space to be reconfigured with a single update of CP15 register 3. In order to ensure that the cache does not represent a leak in the protection system, a cache access must be accompanied by a permission check. This could be achieved by storing the domain and access permission information along with the data in each cache line, but current ARM processors check permissions using information in the MMU concurrently with the cache access. Translation state 312 Architectural Support for Operating Systems 11.9 Input/Output The input/output (I/O) functions are implemented in an ARM system using a combination of memory-mapped addressable peripheral registers and the interrupt inputs. Some ARM systems may also include direct memory access (DMA) hardware. Memory-mapp ed peripherals A peripheral device, such as a serial line controller, contains a number of registers. In a memory-mapped system, each of these registers appears like a memory location at a particular address. (An alternative system organization might have I/O functions in a separate address space from memory devices.) A serial line controller may have a set of registers as follows: A transmit data register (write only); data written to this location gets sent down the serial line. A receive data register (read only); data arriving along the serial line is presented here. A control register (read/write); this register sets the data rate and manages the RTS (request to send) and similar si...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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