If this area of memory is suitably protected it is

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Unformatted text preview: requires the use of one of the special forms of the data processing instruction described in the next section. 118 The ARM Instruction Set Assembler format Examples Notes 1. An SWI may be executed when the processor is already in supervisor mode pro vided the original return address (in r14_svc) and SPSR_svc have been saved; otherwise these registers will be overwritten when the SWI is executed. 2. The interpretation of the 24-bit immediate is system dependent, but most systems support a standard subset for character I/O and similar basic functions. The immediates can be specified as constant expressions, but it is usually better to declare names for the required calls (and set their values) at the start of the program (or import a file which declares their values for the local operating system) and then use these names in the code. To see how to declare names and give them values look at the 'Examples and exercises' on page 72. 3. The first instruction executed in supervisor mode, which is at 08jg, is normally a branch to the SWI handler which resides somewhere nearby in memory. Writing the SWI handler to start at OSjg is not possible because the next memory word, at OC16, is the entry point for the prefetch abort handler. Data processing instructions 119 5.7 Data processing instructions The ARM data processing instructions are used to modify data values in registers. The operations that are supported include arithmetic and bit-wise logical combinations of 32-bit data types. One operand may be shifted or rotated en route to the ALU, allowing, for example, shift and add in a single instruction. Multiply instructions use different formats, so these are considered separately in the next section. Binary encoding register shift length -Figure 5.6 Data processing instruction binary encoding. Description The ARM data processing instructions employ a 3-address format, which means that the two source operands and the destination register are specified independently. One source operand is always a register; the second may be a register, a shifted register or an immediate value. The shift applied to the seco...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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