ARM.SoC.Architecture

In addition to the breakpoint and watchpoint events

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Unformatted text preview: he register is read or written. The address bits specify the particular register following the mapping detailed in Table 8.1. Table 8.1 EmbeddedlCE register mapping. Registers Address 00000 00001 00100 00101 01000 01001 01010 01011 01100 01101 10000 10001 10010 10011 10100 10101 Width 3 5 6 32 32 32 32 32 9 8 32 32 32 32 9 8 Function Debug control Debug status Debug comms control register Debug comms data register Watchpoint 0 address value Watchpoint 0 address mask Watchpoint 0 data value Watchpoint 0 data mask Watchpoint 0 control value Watchpoint 0 control mask Watchpoint 1 address value Watchpoint 1 address mask Watchpoint 1 data value Watchpoint 1 data mask Watchpoint 1 control value Watchpoint 1 control mask The use of the JTAG scan chain is illustrated in Figure 8.18 on page 236. The read or write takes place when the TAP controller enters the 'update DR' state (see Figure 8.15 on page 228). Accessing state The EmbeddedlCE module allows a program to be halted at specific points, but it does not directly allow the processor or system state to be inspected or modified. This is achieved via further scan paths which are also accessed through the JTAG port. 236 Architectural Support for System Development breakpoint Figure 8.18 EmbeddedlCE register read and write structure. Debug comms The mechanism employed to access the processor state is to halt the processor, then to force an instruction such as a store multiple of all the registers into the processor's instruction queue.Then clocks are applied to the processor, again via the scan chain, causing it to write the registers out through its data port. Each register is collected by the scan chain and shifted out. System state is harder to glean, since there may be system locations that cannot be read at the very low speeds that the scan path can generate. Here the processor is preloaded with a suitable instruction, then allowed to access the system location at system speed. This transfers the required system state into a processor register, whereupon it may be passed to the external debugger through the JTAG port as described above. In additions to the breakpoint and watchpoint registers, the EmbeddedlCE module also includes a debug comms port whereby the software ru...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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