In an asynchronous pipeline the stages are all moving

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Unformatted text preview: s is summarized in Table 14.1, which shows the characteristics of the devices manufactured on two different process technologies by European Silicon Systems (ES2) and GEC Plessey Semiconductors (GPS). The layout of the 1 |im AMULET1 core is shown in Figure 14.5. The performance figures, based on the Dhrystone benchmark, show a performance which is of the same order as, but certainly no better than, an ARM6 processor built Table 14.1 AMULET1/ES2 AMULET1 characteristics. AMULET1/GPS 0.7 |im 3.9x2.9 58,374 ~40 kDhrystones3 3 ns/bit 5 V, 20C N/Ab N/A ARM6 1 um 4.1x2.7 33,494 31 kDhrystones 25 ns/bit 5 V, 20 MHz 148 mW 120 Process Area (mm2) Transistors Performance Multiplier Conditions Power MIPS/W 1 um 5.5x4.1 58,374 20.5 kDhrystones 5.3 ns/bit 5 V, 20C 152mW 77 a. Estimated maximum performance, b. The GPS part does not support power measurement. AMULET2 381 Figure 14.5 AMULET1 die plot. on the same process technology. However, AMULET 1 was built primarily to demonstrate the feasibility of self-timed design, which it manifestly does. 14.3 AMULET2 AMULET2 is the second-generation asynchronous ARM processor. It employs an organization which is very similar to that used in AMULET 1, as illustrated in Figure 14.3 on page 378. As described earlier, the two-phase (transition) signalling used on AMULET 1 was abandoned in favour of four-phase (level) signalling. In addition, a number of organizational features were added to enhance performance. AMULET2 register forwarding AMULET2 employs the same register-locking mechanism as AMULET 1, but in order to reduce the performance loss due to register dependency stalls, it also incorporates forwarding mechanisms to handle common cases. The bypass mechanisms used in clocked processor pipelines are inapplicable to asynchronous pipelines, so novel techniques are required. The two techniques used on AMULET2 are: A last result register. The instruction decoder keeps a record of the destination of the result from the execution pipeline, and if the immediately...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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