It can be used to give access to on chip debug

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Unformatted text preview: h some application-specific custom logic. The ARM processor core is itself one such macrocell; the others may come from ARM Limited, a semiconductor partner or some third party supplier. In such cases the designer of the system chip will have limited knowledge of the macrocells and will depend on the macrocell suppliers for the production test patterns for each macrocell. Macrocell testing The JTAG boundary scan test architecture 231 Since the macrocells are buried within the system chip, the designer is faced with the problem of devising a way to apply the supplied test vectors to each of the macro-cells in turn. Test patterns must also be generated for the custom logic part of the design, but the designer is assumed to understand that part of the logic. There are various approaches to getting the test patterns onto the edges of the macrocells: Test modes may be provided which multiplex the signals from each macrocell in turn onto the pins of the system chip. An on-chip bus may support direct test access to each macrocell which is attached to it (see Section 8.2 on page 216). Each macrocell may have a boundary scan path through which the test patterns may be applied using an extension of the JTAG architecture. This last approach is illustrated in Figure 8.16. The chip has a peripheral boundary scan path to support the public EXTEST operation and additional paths around each macrocell, designed into the macrocell, for applying functional tests as supplied. The custom logic designed specifically for this chip may have its own scan path or, as shown in the figure, rely on the fact that all its interface signals must intercept one of the existing scan paths. PCB test scan path Figure 8.16 A possible JTAG extension for macrocell testing. 232 Architectural Support for System Development It should be recognized that although perfectly feasible for functional testing, the scan path approach to macrocell testing has the same drawbacks as using the JTAG boundary scan path to test the core logic on a chip. The serial access is much slower...
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