ARM.SoC.Architecture

It includes a 256 entry colour palette with on chip 8

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Unformatted text preview: et is restricting the video data stream to normal DRAM, whereas high-resolution displays on the standard Rise PC use VRAM. This precludes the use of large numbers of colours on displays with high resolutions, but with LCD displays or monitors of television, VGA or super-VGA resolution the restriction is not apparent. It is only at resolutions of 1,280 x 1,024 and above that the number of colours becomes restricted because of the bandwidth limitations of standard DRAM. The ARM7500 and ARM7500FE 363 Since interactive video and games machines use TV quality displays, and portable computers use liquid crystal displays at VGA (640 x 480 pixel) resolution, the ARM7500 is ideally suited to these applications. Its high integration and power-saving features make it suitable for hand-held test equipment, and its high quality sound and graphics are good characteristics for multimedia applications. ARM7500 silicon A photograph of an ARM7500FE die is shown in Figure 13.11 and the characteristics of the ARM7500 are summarized in Table 13.2. Note the ARM7 core in the upper left-hand corner of the die occupying only 5% of the die area. Figure 13.11 ARM7500FE die photograph. Table 13.2 ARM7500 characteristics. 364 Embedded ARM Applications 13.6 TheARM7100 Figure 13.12 The Psion Series 5MX. The ARM? 100 is a highly integrated microcontroller suited to a range of mobile applications such as smart mobile phones and palm-top computers. It is the basis of the Psion Series 5 range of palm-top computers. A photograph of the Psion Series 5MX (which uses a later version of the 7100 with a modified architecture and a more advanced process technology) is shown in Figure 13.12. ARM7100 organization The organization of the ARM7100 is illustrated in Figure 13.13 on page 365. The ARM710a CPU incorporates an ARM? processor core (a forerunner of the ARM7TDMI, without Thumb support), an ARM memory management unit, an 8 Kbyte 4-way associative quad-word line cache and a 4-address 8-data word write buffer. The use of a cache memory in...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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