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Unformatted text preview: stem functions. The ARM reference peripheral specification defines such a basic set of components, providing a framework within which an operating system can run but leaving full scope for application-specific system extensions. The objective of the reference peripheral specification is to ease the porting of software between compliant implementations and thereby raise the level from which software development begins on a new system. The ARM reference peripheral specification 221 Figure 8.12 AHB multiplexed bus scheme. Base components The reference peripheral specification defines the following components: A memory map which allows the base address of the interrupt controller, the counter timers and the reset controller to vary but defines the offsets of the vari ous registers from these base addresses. An interrupt controller with a defined set of functions, including a defined inter rupt mechanism for a transmit and receive communications channel (though the mechanism of the channel itself is not defined). A counter timer with various defined functions. A reset controller with defined boot behaviour, power-on reset detection, a 'wait for interrupt' pause mode and an identification register. The particular ARM core used with these components is not specified since this does not affect the system programmer's model. 222 Architectural Support for System Development Memory map The system must define the base addresses of the interrupt controller (ICBase), the counter-timer (CTBase) and the reset and pause controller (RPCBase). These addresses are not defined by the reference peripheral specification, but all the addresses of the registers are defined relative to one or other of these base addresses. The interrupt controller provides a uniform way of enabling, disabling and examining the status of up to 32 level-sensitive IRQ sources and one FIQ source. Each interrupt source has a mask bit which enables that source. Memory locations are defined with fixed offsets from ICBase to examine the unmasked, mask and masked interrupt status and to set or clear interrupt sources. Five IRQ sources are defined by the reference peripheral specif...
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- Spring '09