ARM.SoC.Architecture

Later after a judicious modification of the acronym

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Unformatted text preview: chitectures were the Berkeley RISC I and II and the Stanford MIPS (which stands for Microprocessor without Interlocking Pipeline Stages), although some earlier machines such as the Digital PDP-8, the Cray-1 and the IBM 801, which predated the RISC concept, shared many of the characteristics which later came to be associated with RISCs. Features used The ARM architecture incorporated a number of features from the Berkeley RISC design, but a number of other features were rejected. Those that were used were: a load-store architecture; fixed-length 32-bit instructions; 3-address instruction formats. Features rejected The features that were employed on the Berkeley RISC designs which were rejected by the ARM designers were: Register windows. The register banks on the Berkeley RISC processors incorporated a large number of registers, 32 of which were visible at any time. Procedure entry and exit instructions moved the visible 'window' to give each procedure access to new registers, thereby reducing the data traffic between the processor and memory resulting from register saving and restoring. The principal problem with register windows is the large chip area occupied by the large number of registers. This feature was therefore rejected on cost grounds, although the shadow registers used to handle exceptions on the ARM are not too different in concept. In the early days of RISC the register window mechanism was strongly associated with the RISC idea due to its inclusion in the Berkeley prototypes, but subsequently only the Sun SPARC architecture has adopted it in its original form Delayed branches. Branches cause pipelines problems since they interrupt the smooth flow of instructions. Most RISC processors ameliorate the problem by using delayed branches where the branch takes effect after the following instruction has executed. The problem with delayed branches is that they remove the atomicity of individual instructions. They work well on single issue pipelined processors, but they do not scale well to super-s...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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