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Unformatted text preview: ligible in an active circuit. In a welldesigned active circuit the switching power dominates, with the shortcircuit power adding perhaps 10% to 20% to the total power, and the leakage current being significant only when the circuit is inactive. However, the trend to lower voltage operation does lead to a tradeoff between performance and leakage current as discussed further below, and leakage is an increasing concern for future lowpower highperformance designs. CMOS circuit power The total power dissipation, Pc, of a CMOS circuit, neglecting the shortcircuit and leakage components, is therefore given by summing the dissipation of every gate g in the circuit C: 30 An Introduction to Processor Design where/is the clock frequency, Ag is the gate activity factor (reflecting the fact that not all gates switch every clock cycle) and C/ is the gate load capacitance. Note that within this summation clock lines, which make two transitions per clock cycle, have an activity factor of 2. Lowpower circuit design The typical gate load capacitance is a function of the process technology and therefore not under the direct control of the designer. The remaining parameters in Equation 3 suggest various approaches to lowpower design. These are listed below with the most important first: 1. Minimize the power supply voltage, Vdd. The quadratic contribution of the supply voltage to the power dissipation makes this an obvious target. This is discussed further below. 2. Minimize the circuit activity, A. Techniques such as clock gating fall under this heading. Whenever a circuit function is not needed, activity should be eliminated. 3. Minimize the number of gates. Simple circuits use less power than complex ones, all other things being equal, since the sum is over a smaller number of gate contributions. 4. Minimize the clock frequency, f. Avoiding unnecessarily high clock rates is clearly desirable, but although a lower clock rate reduces the power consumption it also reduces performance, hav...
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 Spring '09
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