Memory bandwidth the performance of a processor is

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Unformatted text preview: the segmented CAM-RAM organization, at least in part to facilitate the support of cache lock-down (discussed further in Example 12.1 on page 346). Cache write strategy Write-through caches are the simplest to design, and they cope well when the processor clock rate is a small multiple of the main memory cycle rate. Once the processor clock rises to ten or more times the memory cycle rate, the write data traffic generated by data store instructions will begin to saturate the external memory bus and the processor will frequently be stalled waiting for write cycles to complete. The only way around this problem is to use a cache strategy that does not result in all writes passing to main memory, for example by implementing a copy-back cache. Current main memory will typically cycle at around 10 MHz, so the ARM? series of CPUs can operate satisfactorily at 60 Mhz with a write-through cache. The ARMS 10 is borderline at its first design clock rate, but had it not been superseded by the ARM9 series it would have been taken to higher clock rates and was therefore designed with a copy-back cache. Caches for the ARM9 and ARM 10 must employ a copy-back strategy if their performance is not to be compromised. Longer cache lines reduce the size of the tag store (for a given data store size), reduce the cache miss rate and increase the miss cost (the time taken to load a cache line). The ARM CPU cores all use either a quad-word (16-byte) or an 8-word (32-byte) line, the smaller size being preferred for the smaller caches and embedded code and the larger size for larger caches and general-purpose code. The 64-bit buses used on the ARM1020E allow a 32-byte cache line to be loaded and flushed in the same number of memory cycles as a 16-byte line requires with a 32-bit bus. The ARM MMU is a sophisticated unit that occupies a similar silicon area to the processor core itself. Where its functionality is needed it must be included. Any general-purpose system where the mix of application code is unknown at design time proba...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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