ARM.SoC.Architecture

Memory granularity the memory mapping is performed at

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Unformatted text preview: describing the status of the current program with respect to each domain. The interpretation of the two bits is given in Table 11.4. The relationship of a program to all of the domains can be changed by writing a single new value into CP15 register 3. Translatio n process The translation of a new virtual address always begins with a first-level fetch. (We ignore for now the TLB, which is only a cache to accelerate the process described below.) This uses the translation base address held in CP15 register 2. Bits [31:14] of the translation base register are concatenated with bits [31:20] of the virtual address to form a memory address which is used to access the first-level descriptor as shown in Figure 11.3 on page 304. The first-level descriptor may be either a section descriptor or a pointer to a second-level page table depending on its bottom two bits. '01' indicates a pointer to a second-level coarse page table; '10' indicates a section descriptor; '11' indicates a pointer to a second-level fine page table (only supported by certain CPUs). '00' should be used to indicate a descriptor that causes a translation fault. Where the first-level descriptor indicates that the virtual address translates into a section, the domain ('Domain' in the section descriptor) is checked and, if the current process is a client of the domain, the access permissions ('AP' in the section descriptor) are also checked. If the access is permissible, the memory address is formed by concatenating bits [31:20] of the section descriptor with bits [19:0] of the Section translation 304 Architectural Support for Operating Systems Figure 11.3 First-level translation fetch. virtual address. This address is used to access the data in memory. The full section translation sequence is shown in Figure 11.4 on page 305. The operation of the access permission bits (AP) is described in 'Access permissions' on page 305, and the operation of the bufferable (B) and cacheable (C) bits is described in 'Cache and write buffer control' on page 308. Page translation Where the first-level descriptor indicates that the virtual addres...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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