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Unformatted text preview: buffer smooths out small peaks in the write data bandwidth, decoupling the processor from stalls caused by the memory bus saturating. A large peak that causes the buffer to fill will stall the processor. Independent writes to the same 16-byte area are merged within the write buffer, though only to the last address written into the buffer. The buffer stores up to eight addresses (each address aligned to a 16-byte boundary), copying the virtual address for use when merging writes and the physical address to address the external memory, and up to 16 bytes of data for each address (so each address can handle a dirty half-line or up to four registers from a single store multiple). The write buffer 334 ARM CPU Cores The write buffer may be disabled by software, and individual memory regions may be marked as bufferable or unbufferable using the MMU page tables. All cacheable regions are bufferable (evicted cache lines are written through the write buffer) but uncacheable regions may be bufferable or unbufferable. Normally the I/O region is unbufferable. An unbuffered write will wait for the write buffer to empty before it is written to memory. Data reads that miss the data cache are checked against entries in the write buffer to ensure consistency, but instruction reads are not checked against the write buffer. Whenever memory locations which have been used as data are to be used as instructions a special instruction should be used to ensure that the write buffer has drained. MMU organization StrongARM incorporates the standard ARM memory management architecture, using separate translation look-aside buffers (TLBs) for instructions and data. Each TLB has 32 translation entries arranged as a fully associative cache with cyclic replacement. A TLB miss invokes table-walking hardware to fetch the translation and access permission information from main memory. A photograph of a StrongARM die is shown in Figure 12.10 with an overlay indicating the major functional areas. The die area is, not surprisingly, dominated by the instruction cache (1CACHE) and the data cache (DCACHE). Each cache has its own MMU (IMMU and DMMU). The processor core has the instruction...
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- Spring '09