ARM.SoC.Architecture

Needless to say this redundancy was not carried

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: e the processor is halted, the MMU has time to control the generation of the abort signal. A set-associative cache, on the other hand, will usually produce its hit/miss signal at the end of the cycle, too late to defer a miss to the MMU (which may generate an abort) without a significant performance loss. (The ARM? 10, which has a set-associative RAM-RAM cache, does not follow this rule, and the cache still generates its hit/miss signal and the MMU its protection information before the end of phase 1.) In order to ease the constraints on the cache and MMU designs, later ARMs were redesigned to allow aborts to be flagged at the end of the cycle, with a similar timing to Abort timing ARM architecture variants 147 the read data. The compromise that had to be accepted was that now the processor state has changed further so there is more work for the abort recovery software to do. Some ARM processors may be configured (by external hard-wiring or using the L bit, bit 6 of CP15 register 1, see Section 11.2 on page 293) to work with either early or late abort timing. ARM data aborts The state of the ARM after a data abort depends on the particular processor and, with some processors, on the early/late abort configuration: In all cases the PC is preserved (so on data abort exception entry r14_abt con tains the address of the faulting instruction plus eight bytes). The base register will either be unmodified, or will contain a value modified by auto-indexing (it will not be overwritten by a loaded value). Other load destination registers may have been overwritten, but the correct value will be loaded when the instruction is retried. Because the base register may be modified by auto-indexing, certain (not very useful) auto-indexing modes should be avoided. For example: LDR r0, [r1], rl This instruction uses r1 as the address for the load, then uses post-indexing to add r1 to itself, losing the top bit in the process. If, following a data abort, only the modified value of r1 is available, it is not possible to recover the...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online