ARM.SoC.Architecture

Normal instruction execution uses instructions stored

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Unformatted text preview: on mechanism ensures that user code cannot gain supervisor privileges without appropriate checks being carried out to ensure that the code is not attempting illegal operations. The upshot of this for the user-level programmer is that system-level functions can only be accessed through specified supervisor calls. These functions generally include any accesses to hardware peripheral registers, and to widely used operations such as character input and output. User-level programmers are principally concerned with devising algorithms to operate on the data 'owned' by their programs, and rely on the operating system to handle all transactions with the world outside their programs. The instructions which request operating system functions are covered in 'Supervisor calls' on page 67. All ARM instructions are 32 bits wide (except the compressed 16-bit Thumb instructions which are described in Chapter 7) and are aligned on 4-byte boundaries in memory. Basic use of the instruction set is described in Chapter 3 and full details, including the binary instruction formats, are given in Chapter 5. The most notable features of the ARM instruction set are: The load-store architecture; 3-address data processing instructions (that is, the two source operand registers and the result register are all independently specified); conditional execution of every instruction; the inclusion of very powerful load and store multiple register instructions; the ability to perform a general shift operation and a general ALU operation in a single instruction that executes in a single clock cycle; open instruction set extension through the coprocessor instruction set, including adding new registers and data types to the programmer's model; a very dense 16-bit compressed representation of the instruction set in the Thumb architecture. To those readers familiar with modern RISC instruction sets, the ARM instruction set may appear to have rather more formats than other commercial RISC processors. While this is certainly the case and it does lead to more complex instruction decoding, it also leads to higher code density. For the small embedded systems that most ARM processors are used in, this code density advantage outweighs the small performance penalty incurred by the decode complexity. T...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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