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Unformatted text preview: e and very fast. If the memory is too small, it will not be able to hold enough programs to keep the processor busy. If it is too slow, the memory will not be able to supply instructions as fast as the processor can execute them. Unfortunately, the larger a memory is the slower it is. It is therefore not possible to design a single memory which is both large enough and fast enough to keep a high-performance processor busy. It is, however, possible to build a composite memory system which combines a small, fast memory and a large, slow main memory to present an external behaviour which, with typical program statistics, appears to behave like a large, fast memory much of the time. The small, fast memory component is the cache, which automatically retains copies of instructions and data that the processor is using most frequently. The effectiveness of the cache depends on the spatial locality and temporal locality properties of the program. This two-level memory principle can be extended into a memory hierarchy of many levels, and the computer backup (disk) store can be viewed as part of this hierarchy. With suitable memory management support, the size of a program is limited not by the computer's main memory but by the size of the hard disk, which may be very much larger than the main memory.
269 270 Memory Hierarchy 10.1 Memory size and speed
A typical computer memory hierarchy comprises several levels, each level having a characteristic size and speed. The processor registers can be viewed as the top of the memory hierarchy. A RISC processor will typically have around thirty-two 32-bit registers making a total of 128 bytes, with an access time of a few nanoseconds. On-chip cache memory will have a capacity of eight to 32 Kbytes with an access time around ten nanoseconds. High-performance desktop systems may have a second-level off-chip cache with a capacity of a few hundred Kbytes and an access time of a few tens of nanoseconds. Main memory will be megabytes to tens of megabytes of dynamic RAM with an access...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09