ARM.SoC.Architecture

Note that as the target is an arm instruction the

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Unformatted text preview: half-word (2-byte) offsets. Therefore there is no direct mapping from these Thumb instructions into the ARM instruction set. The ARM cores that support Thumb are slightly modified to support half-word branch offsets, with ARM branch instructions being mapped to even half-word offsets. 194 The Thumb Instruction Set Format 4 is equivalent to the ARM instruction with the same assembler syntax. The BLX variant is supported only by ARM processors that implement architecture v5T. Subroutine call and return The above instructions, and the equivalent ARM instructions, allow for subroutine calls to functions written in an instruction set the same as, or opposite to, the caller. Functions that are called only from the same instruction set can use the conventional BL call and MOV pc, r14 or LDMFD sp!, {. . ,pc) (in Thumb code, POP {. . ., pc}) return sequences. Functions that can be called from the opposite instruction set or from either instruction set can return with BX lr or LDMFD sp!, {. . . ,rN}; BX rN (in Thumb code, POP { . . . , rN} ; BX rN). ARM processors that support architecture v5T can also return with LDMFD sp!, {. . ., pc} (in Thumb code, POP {. . ., pc}) as these instructions use the bottom bit of the loaded PC value to update the Thumb bit, but this is not supported in architectures earlier than v5T. 7.4 Thumb software interrupt instruction The Thumb software interrupt instruction behaves exactly like the ARM equivalent and the exception entry sequence causes the processor to switch to ARM execution. Binary encoding Figure 7.3 Thumb software interrupt binary encoding. Description This instruction causes the following actions: The address of the next Thumb instruction is saved in r14_svc. The CPSR is saved in SPSR_svc. The processor disables IRQ, clears the Thumb bit and enters supervisor mode by modifying the relevant bits in the CPSR. The PC is forced to address 0x08. The ARM instruction SWI handler is then entered. The normal return instruction restores the Thumb execution state. Assembler format SWI <8-bit immediate> Thumb data processing instruct...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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