ARM.SoC.Architecture

Note that not all bits are provided in all

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Unformatted text preview: as of the cache. (The ARM740T uses certain bits in register 1 for this purpose.) Register 15 is used in the ARM940T to modify the cache allocation algorithm from random to round-robin. This is intended for use only during silicon production testing. 11.4 ARM protection unit ARM CPUs intended for embedded applications incorporate a memory protection unit which defines various protection and cache functions for different regions of memory so that, for example, I/O regions can be restricted to supervisor access only and made uncacheable. Protection units do not translate addresses. Systems which require address translation should use a full memory management unit, described in Section 11.6 on page 302. CPUs which incorporate the protection unit include the ARM740T and the ARM940T. Protection unit structure The protection unit allows the ARM 4 Gbyte address space to be mapped into eight regions, each with a programmable start address and size and with programmable protection and cache properties. The regions may overlap. A fixed priority scheme defines those characteristics which apply to an address which falls into more than one region. Each of the eight regions has a start address and a size defined by writing to CP15 register 6. The format of this register was defined on page 296. The minimum region size is 4 Kbytes, the maximum 4 Gbytes. Rd[5:l], when written to CP15 register 6, defines the size, which can be set to any power of two bytes between the maximum and minimum as shown in Table 11.2 on page 298. The start address must be a multiple of the selected size and is defined by Rd[31:12]. The region will have no effect unless it is enabled by setting Rd[0]. The regions may legitimately be programmed so that they overlap. When an address that falls into more than one region is presented to the protection unit a fixed priority scheme determines which region defines its attributes: region 7 has the highest priority, region 0 the lowest, and the other regions have intermediate priorities in order of their number. Region def...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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