ARM.SoC.Architecture

Note that this is the only reason for including swap

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Unformatted text preview: does re-enable interrupts, it may be necessary to save and restore some of the privileged mode registers as well. The 'architectural support' for register saving and restoring offered on the ARM recognizes the difficulty of saving and restoring user registers from a privileged mode and provides special instructions to assist in this task. These instructions are the special forms of the load and store multiple instructions (see Section 5.12 on page 130) which allow code running in a non-user mode to save and restore the user registers from an area of memory addressed by a non-user mode register. Context switching 311 Without these instructions, an operating system would have to switch into user mode to save or restore the banked user registers and then get back through the protection barrier into supervisor mode. Though possible, this solution is inefficient. Floating-point state The floating-point registers, whether held in a hardware coprocessor or maintained in memory by a software emulator, represent part of the state of any process that uses them. Rather than add to the context switching overhead by saving and restoring them on every process swap, the operating system simply disables user-level use of the floating-point system when a process that uses floating-point is swapped out. If the new process attempts to use the floating-point system, the first use will trap. At that point the operating system will save the old process state and restore the new, then it will re-enable the floating-point system and the new process can use it freely. Thus the floating-point context switch overhead is incurred only when strictly necessary. Where the old and new processes have independent translation tables a heavy-weight process switch is required. The complete translation table structure can be switched simply by changing the base address of the first-level page table in CP15 register 2, but since this will invalidate existing TLB and (virtually addressed) cache entries, these must be flushed. The TLB and an...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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