ARM.SoC.Architecture

Only those bits of the address that are not used to

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Unformatted text preview: hit on both. The 8 Kbyte cache with 16 byte lines will have 256 lines in each half of the cache, so four bits of the 32-bit address select a byte from the line and eight bits select one line from each half of the cache. The address tag must therefore be one bit longer, at 276 Memory Hierarchy Figure 10.4 Two-way set-associative cache organization. 20 bits. The access time is only very slightly longer than that of the direct-mapped cache, the increase being due to the need to multiplex the data from the two halves. When a new data item is to be placed in the cache, a decision must be taken as to which half to place it in. There are several options here, the most common being: Caches 277 Random allocation. The decision is based on a random or pseudo-random value. Least recently used (LRU). The cache keeps a record of which location of a pair was last accessed and allocates the new data to the other one. Round-robin (also known as 'cyclic'). The cache keeps a record of which location of a pair was last allocated and allocates the new data to the other one. The set-associative approach extends beyond 2-way up to any degree of associativity, but in practice the benefits of going beyond 4-way associativity are small and do not warrant the extra complexity incurred. The fully associative cache At the other extreme of associativity, it is possible to design a fully associative cache in VLSI technology. Rather than continuing to divide the direct-mapped cache into ever smaller components, the tag store is designed differently using content addressed memory (CAM). A CAM cell is a RAM cell with an inbuilt comparator, so a CAM based tag store can perform a parallel search to locate an address in any location. The organization of a fully associative cache is illustrated in Figure 10.5. 278 Memory Hierarchy Since there are no address bits implicit in the position of data in the cache, the tag must store all the address bits apart from those used to address bytes within the line. Write strategies The above sc...
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