ARM.SoC.Architecture

# Plus or minus infinity are represented by the maximum

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Unformatted text preview: that for single precision values, but now the exponent bias for normalized numbers is +1023: Figure 6.3 IEEE 754 double precision floating-point number format. Double extended precision Even greater accuracy is available from the double extended precision format, which uses 80 bits of information spread across three words. The exponent bias is 16383, and the J bit is the bit to the left of the binary point (and is a T for all normalized numbers): Figure 6.4 IEEE 754 double extended precision floating-point number format. Packed decimal In addition to the binary floating-point representations detailed above, the IEEE 754 standard also specifies packed decimal formats. Referring back to Equation 13 on page 158, in these packed formats b is 10 and a and n are stored in a binary coded decimal format as described in 'Binary coded decimal' on page 154. The number is normalized so that 1 < a < 10 . The packed decimal format is shown on page 162: 162 Architectural Support for High-Level Languages Figure 6.5 IEEE 754 packed decimal floating-point number format. The sign of the exponent is held in bit 31 of the first word ('E') and the sign of the decimal in bit 30 ('D'). The value of the number is: value (packed) = (-1) x decimal x 1 o"'1>*x exponent) Equation 17 Extended packed decimal The extended packed decimal format occupies four words to give higher precision. The value is still as given by Equation 17 above and the format is: Figure 6.6 IEEE 754 extended packed decimal floating-point number format. ARM floatingpoint instructions Although there is no direct support for any of these floating-point data types in a standard ARM integer core, ARM Limited has defined a set of floating point instructions within the coprocessor instruction space. These instructions are normally implemented entirely in software through the undefined instruction trap (which collects any coprocessor instructions that are not accepted by a hardware coprocessor), but a subset may be handled in hardware by the...
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## This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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