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Unformatted text preview: speed of the device to check its performance. Therefore the JTAG architecture is not a generic solution to all the problems of VLSI production testing. However, it can solve a number of problems: The JTAG port can be used for in-circuit functional testing of an 1C (provided that the INTEST instruction is supported). It gives good control of the 1C pins for parametric testing (checking the drive of the output buffers, leakage, input thresholds, and so on). This uses only the EXTEST instruction which is required on all JTAG compliant devices. It can be used to access internal scan paths to improve the controllability and observability of internal nodes that are hard to access from the pins. It can be used to give access to on-chip debug functions with no additional pins and without interfering with the system functions. This is exploited by the ARM EmbeddedlCE debug architecture described briefly below and in detail in Section 8.7 on page 232. It offers an approach to the functional testing of macrocell-based designs as described below. These uses are all in addition to its principal purpose, which is in the production testing of printed circuit boards. Embedded-ICE The ARM debug architecture, described in Section 8.7 on page 232, is based on an extension of the JTAG test port. The EmbeddedlCE module introduces breakpoint and watchpoint registers which are accessed as additional data registers using special JTAG instructions, and a trace buffer which is similarly accessed. The scan path around the ARM core macrocell is used to introduce instructions into the ARM pipeline without interfering with other parts of the system and these instructions can be used to access and modify the ARM and system state. The debug architecture gives most of the functionality of a conventional In-Circuit Emulation system to debug an ARM macrocell on a complex system chip, and since the JTAG test access port is used to control the debug hardware, no additional pins are required on the chip. A growing trend in the design of complex system chips is to incorporate a number of complex, pre-designed macrocells, together wit...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09