ARM.SoC.Architecture

Processor and memory speeds in 1980 a typical dram

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: an a fixed partitioning. On the other hand the separate caches allow load and store instructions to execute in a single clock cycle. Unified and Harvard caches Caches 273 Figure 10.1 A unified instruction and data cache. Cache performance metrics Since the processor can operate at its high clock rate only when the memory items it requires are held in the cache, the overall system performance depends strongly on the proportion of memory accesses which cannot be satisfied by the cache. An access to an item which is in the cache is called a hit, and an access to an item which is not in the cache is a miss. The proportion of all the memory accesses that are satisfied by the cache is the hit rate, usually expressed as a percentage, and the proportion that are not is the miss rate. The miss rate of a well-designed cache should be only a few per cent if a modern processor is to fulfil its potential. The miss rate depends on a number of cache parameters, including its size (the number of bytes of memory in the cache) and its organization. Since a cache holds a dynamically varying selection of items from main memory, it must have storage for both the data and the address at which the data is stored in main memory. The simplest organization of these components is the direct-mapped cache which is illustrated in Figure 10.3 on page 275. In the direct-mapped cache a line of data is stored along with an address tag in a memory which is addressed by some portion of the memory address (the index). To check whether or not a particular memory item is stored in the cache, the index address bits are used to access the cache entry. The top address bits are then compared Cache organization The direct-mapped cache 274 Memory Hierarchy Figure 10.2 Separate data and instruction caches. with the stored tag; if they are equal, the item is in the cache. The lowest address bits can be used to access the desired item within the line. This, simplest, cache organization has a number of properties that can be...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online