See pc behaviour on page 78 for an explanation of the

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: tine. Format (1) instructions may be executed conditionally or unconditionally, but format (2) instructions are executed unconditionally. Assembler format 1: 2: B{L}X{<cond>} Rm BLX <target address> '<target address>' is normally a label in the assembler code; the assembler will generate the offset (which will be the difference between the word address of the target and the address of the branch instruction plus 8) and set the H bit if appropriate. Examples Software Interrupt (SWI) 117 Notes 1. Some ARM processors which do not support the Thumb instruction set will trap these instructions, allowing software emulation of Thumb. 2. Only processors that implement ARM architecture v5T support either format of the BLX instruction (see Section 5.23 on page 147). 5.6 Software Interrupt (SWI) The software interrupt instruction is used for calls to the operating system and is often called a 'supervisor call'. It puts the processor into supervisor mode and begins executing instructions from address 0x08. If this area of memory is suitably protected it is possible to build an operating system on the ARM that is fully protected from a malicious user, though since ARM is rarely used in multi-user applications this level of protection is not often sought. Binary encoding Figure 5.5 Software interrupt binary encoding. Description The 24-bit immediate field does not influence the operation of the instruction but may be interpreted by the system code. If the condition is passed the instruction enters supervisor mode using the standard ARM exception entry sequence. In detail, the processor actions are: 1. Save the address of the instruction after the SWI in r14_svc. 2. Save the CPSR in SPSR_svc. 3. Enter supervisor mode and disable IRQs (but not FIQs) by setting CPSR[4:0] to 10011 2 andCPSR[7]tol. 4. Set the PC to 08 ]6 and begin executing the instructions there. To return to the instruction after the SWI the system routine must not only copy r14_svc back into the PC, but it must also restore the CPSR from SPSR_svc. This...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online