ARM.SoC.Architecture

Signals that specify the direction rw and size bw on

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: us pins D[31:24] which are connected to the ARM's pins D[31:24]. Since the bottom two address lines, A [1:0], are used for byte selection, they are used by the control logic and not connected to the memory. Therefore the address lines on the memory devices are connected to A [2] and upwards, the precise number used depending on the size of the memory part (for example, a 128 Kbyte ROM part will useA[18:2J). The ARM memory interface 209 Figure 8.1 A basic ARM memory system. Although the ARM performs reads of both bytes and words, the memory system can ignore the difference (at the cost of some power wastage) and always simply supply a word quantity. The ARM will extract the addressed byte and ignore the remainder of the word. Therefore the ROMs do not need individual enables and using 16-bit devices causes no problems. Byte writes, however, do require individual byte enables, so the control logic must generate four byte write enable controls. This makes the use of wider RAMs difficult (and inefficient) unless they incorporate separate byte enables, since writing an individual byte would require a read-modify-write memory operation. Since many processors require support for writing bytes, it is likely that if RAMs do become available with a data width greater than a byte, they will incorporate individual byte enables. Control logic The control logic performs the following functions: It decides when to activate the RAM and when to activate the ROM. This logic determines the system memory map. The processor starts from location zero after a reset, so it must find ROM there since the RAM is uninitialized. The simplest memory map therefore enables the ROM ifAf31J is low and the RAM if it is high. (Most ARM systems change the memory map shortly after 210 Architectural Support for System Development start-up to put the RAM at the bottom of memory so that the exception vectors can be modified.) It controls the byte write enables during a write operation. During a word write all the byte enables should be active, during a byte write only the addresse...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online