ARM.SoC.Architecture

Similar limitations to those on the word and unsigned

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Unformatted text preview: on includes a bit for each visible register, with bit 0 controlling whether or not r0 is transferred, bit 1 controls r1, and so on up to bit 15 which controls the transfer of the PC. The registers are loaded from or stored to a contiguous block of memory words defined by the base register and the addressing mode. The base address will be incremented (U = 1) or decremented (U = 0) before (P = 1) or after (P = 0) each word transfer. Auto-indexing is supported; if W = 1 the base register will be increased (U = 1) or decreased (U = 0) by the number of bytes transferred when the instruction completes. Special forms of the instruction allow it to be used to restore the CPSR: if the PC is in the register list of a load multiple and the S bit is set, the SPSR of the current mode will be copied into the CPSR, giving an atomic return and restore state instruction. This form should not be used in user mode code since there is no SPSR in user mode. If the PC is not in the register list and the S bit is set, both load and store multiple instructions executed in non-user modes will transfer the user mode registers (while using the current mode base register). This allows an operating system to save and restore user process state. The normal form of the instruction is: LDMISTM{<cond>}<add mode> Rn{!}, <registers> Assembler format where odd mode> specifies one of the addressing modes detailed in Table 3.1 on page 62. The instruction bits correspond closely to the mechanistic view described in this table, with 'increment' corresponding to U = 1 and 'before' corresponding to P = 1. '!' specifies auto-indexing (W = 1), and <registers> is a list of registers and register ranges enclosed in curly brackets, for example: {r0, r3-r7, pc}. In a non-user mode, the CPSR may be restored by: LDM{<cond>}<add mode> R n { ! } , <registers + pc>^ The register list must contain the PC. In a non-user mode, the user registers may be saved or restored by: LDM I STM{&l...
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