ARM.SoC.Architecture

So the era of complex systems on a single chip is

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Unformatted text preview: is available at any time, and byte-wide FIFO buffers decouple the processor from having to respond to every byte which is transferred. A synchronous communications controller module supports a range of standard serial communication protocols, and a serial controller module provides a software-controlled data port which can be used to implement various serial control protocols such as the I2C bus defined by Philips which enables a range of serial devices such as battery-backed RAM, real-time clock, E2PROM and audio codecs to be connected. The external bus interface supports devices with 8-, 16- and 32-bit data buses and has flexible wait state generation. The counter-timer block has three 8-bit counters connected to a 24-bit prescaler, and an interrupt controller gives programmable control of all on- and off-chip interrupt sources. The chip has four power-management modes: 1. On-line - all circuits are clocked at full speed. 2. Command - the ARM core runs with 1 to 64 wait states but all other circuitry runs at full speed. An interrupt switches the system into on-line mode immediately. 3. Sleep - all circuitry is stopped apart from the timers and oscillators. Particular interrupts return the system to on-line mode. 4. Stopped - all circuits (including the oscillators) are stopped. Particular interrupts return the system to on-line mode. Packaging The Ruby II is available in 144- and 176-pin thin quad flat packs and can operate at up to 32 MHz at 5 volts. At 20 MHz using 32-bit 1 wait state memory the chip consumes 30 mA in on-line mode, 7.9 mA in command mode, 1.5 mA in sleep mode and 150 uA in stop mode. The VLSI ISDN Subscriber Processor 349 Figure 13.1 Ruby II advanced communication controller organization. 13.2 The VLSI ISDN Subscriber Processor The VLSI ISDN Subscriber Processor (VIP) is a programmable engine for ISDN (Integrated Services Digital Network; a digital telephony standard) subscriber communications. The design was developed by Hagenuk GmbH for use in their ISDN product range and subsequently licensed back to VLSI Technology for...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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