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Unformatted text preview: of fault and the domain of the last data access that aborted. D is set on a data breakpoint. Register 6 (which is read-write in architecture version 4, but in version 3 it is read-only and writing to it flushes a particular TLB entry) contains the address of the last data access that aborted. Register 7 (which is read-write in architecture version 4, but in version 3 it is write-only and simply flushes the cache) is used to perform a number of cache, write buffer, prefetch buffer and branch target cache clean and/or flush oper ations. The data supplied should be either zero or a relevant virtual address. Accesses to register 7 use the Cop2 and CRm fields to specify particular operations; the available functions vary from implementation to implementation. Register 8 (which is read-write in architecture version 4 and unavailable in ver sion 3) is used to perform a number of TLB operations, flushing single entries or the whole TLB and supporting unified or separate instruction and data TLBs. Register 9 is used to control the read buffer, if one is present. In some CPUs it is used to control cache lockdown functions. Register 10 is used to control TLB lockdown functions where these are sup ported. Register 13 is used to remap virtual addresses through a process ID register. This mechanism is used to support Windows CE and is only present on particular 302 Architectural Support for Operating Systems CPUs such as the ARM720T, the ARM920T and the S A-1100. If bits [31:25] of the virtual address are zero they are replaced with bits [31:25] of this register. Register 14 is used for debug support. Register 15 is used for test and in some CPUs for clock control purposes. 11.6 ARM MMU architecture
An MMU performs two primary functions: It translates virtual addresses into physical addresses. It controls memory access permissions, aborting illegal accesses. The ARM MMU uses a 2-level page table with table-walking hardware and a TLB which stores recently used page translations. Where the processor has separate instruction and data caches it is likely a...
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- Spring '09