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Unformatted text preview: an 8-bit parallel port with handshake capability; 2 general-purpose pulse-width modulation controllers; an on-chip clock oscillator produces 38.864 MHz, and on-chip phase-locked loops produce the 12.288 MHz master clock required by the ISDN interface and the 13.824 MHz master clock required by the DECT controller; DRACO functions 392 The AMULET Asynchronous ARM Processors an ISDN-DECT synchronizer phase-locked loop avoids bit loss in data transfers between the ISDN and DECT clock domains; the clock system has power-down features. In addition, the self-timed AMULET3H processing subsystem incorporates: a 100 MIPS AMULET3 32-bit processor that implements ARM architecture v4T (including the Thumb 16-bit compressed instruction set) with debug hardware; 8 Kbytes of dual-port high-speed RAM (local to the processor); a self-timed on-chip bus with a bridge to the synchronous on-chip bus that con nects the synchronous peripherals; a 32-channel DMA controller; 16 Kbytes of ROM holding standard telecommunications application software; an asynchronous event driven load module that holds the processor in zero-power wait mode while an analogue-to-digital conversion completes, thereby synchro nizing the software to external data rates; a programmable external memory interface that supports the direct connection of SRAM, DRAM and flash memory; an on-chip reference delay line calibrated by software to control off-chip memory access timings. AMULET3H AMULET3H is a subsystem based around an AMULET3 core that forms an asynchronous 'island' at the heart of the DRACO telecommunications controller in which it is interfaced to a range of synchronous peripheral controllers. To reap the benefits of asynchronous operation the core must have access to some memory that operates asynchronously, and there are significant electromagnetic compatibility benefits in having off-chip memory also operate asynchronously. The organization of the asynchronous subsystem is illustrated in Figure 14.12 on page 393. The AMULET3 core is connected directly to a dual-ported RAM (discussed further below) and then to the MARBLE on-chip bus. MARBLE is similar in concept to ARM's AMBA bus, the major difference being that it does not use a clock signal. Its transfer mechanism is based around a split transaction primitive. System components other than the local RAM are accessed via the MARBLE bus. These include on-chip ROM, a DMA controller, a bridge to the synchronous bus where the application-specific perip...
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- Spring '09