The arm 10200 is intended to be used for the

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Unformatted text preview: von Neumann architecture (that is, it has a single memory port used for both instruc tion and data transfers), a unified cache can support its memory bandwidth requirements. The ARM710T, 720T and 740T all include such a cache. The ARM9TDMI requires more than one word of data per clock cycle and employs a Harvard architecture (separate instruction and data memory ports) to achieve this. Separate caches (and memory management units) can satisfy its needs. The ARM920T and 940T incorporate separate 32-bit caches. The ARM10TDMI requires more than one instruction per clock cycle as it attempts to predict and remove branches before they enter the execution unit. It also transfers two data words per cycle during load and store multiple instruc tions. It therefore requires separate caches each wider than 32 bits, such as the 64-bit caches in the ARM1020E. The separate caches used on the ARM9 and ARM 10 series of CPUs can lead to coherency problems which are left to software to resolve. Alternative ways to provide the necessary bandwidth are illustrated by the double-bandwidth cache of the ARMS 10 and the dual-ported local memory on the AMULET3H subsystem (described in Section 14.6 on page 390). Both of these approaches use a unified memory model which simplifies software design but at the cost of somewhat more complex hardware. Cache associativity The relative merits of set-associative RAM-RAM caches and fully associative CAM-RAM caches have been discussed at length in this chapter and in Chapter 10. The earliest ARM CPU designs adopted the segmented CAM-RAM structure for a combination of performance and power-efficiency reasons. The ARM7 series of CPUs switched to a 4-way set-associative RAM-RAM organization principally because RAM is smaller than CAM (it requires about half the layout area per bit) and is more generally available in the standard design libraries of the many target processes that Discussion 345 the ARM must address. The later ARMS, ARM9 and ARM 10 CPUs have reverted to...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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