The arm coprocessor interface 101 the choice between

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Unformatted text preview: ssors through the undefined instruction trap. Coprocessor architecture The coprocessor architecture is described in Section 5.16 on page 136. Its most important features are: Support for up to 16 logical coprocessors. Each coprocessor can have up to 16 private registers of any reasonable size; they are not limited to 32 bits. Coprocessors use a load-store architecture, with instructions to perform internal operations on registers, instructions to load and save registers from and to memory, and instructions to move data to or from an ARM register. The simpler ARM cores offer the coprocessor interface at board level, so a coprocessor may be introduced as a separate component. High clock speeds make board-level interfacing very difficult, so the higher-performance ARMs restrict the coprocessor interface to on-chip use, in particular for cache and memory management control functions, but other on-chip coprocessors may also be supported. ARM7TDMI coprocessor interface The ARM7TDMI coprocessor interface is based on 'bus watching' (other ARM cores use different techniques). The coprocessor is attached to a bus where the ARM instruction stream flows into the ARM, and the coprocessor copies the instructions into an internal pipeline that mimics the behaviour of the ARM instruction pipeline. As each coprocessor instruction begins execution there is a 'hand-shake' between the ARM and the coprocessor to confirm that they are both ready to execute it. The handshake uses three signals: 1. cpi (from ARM to all coprocessors). This signal, which stands for 'Coprocessor Instruction', indicates that the ARM has identified a coprocessor instruction and wishes to execute it. 102 ARM Organization and Implementation 2. cpa (from the coprocessors to ARM). This is the 'Coprocessor Absent' signal which tells the ARM that there is no coprocessor present that is able to execute the current instruction. 3. cpb (from the coprocessors to ARM). This is the 'CoProcessor Busy' signal which tells the ARM that t...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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